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 * Copyright (c) 2021, Infineon Technologies AG
 *
 * 
 * Distributed under the Boost Software License, Version 1.0.
 * 
 * 
 * Boost Software License - Version 1.0 - August 17th, 2003
 * 
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/********************************************************************************************************
 * @file        TLE926x_ISR.h
 *
 * @brief       Declaration file for ISR-Vectors and ISR related functions
 *
 * @version     V1.0.0
 * @date        
 * @author      Fedy Farhat
 * @author      Michael Schaffarczyk
 ********************************************************************************************************/


#ifndef TLE926x_ISR_H
#define TLE926x_ISR_H



/* ================================================================================ */
/* ============================   HEADER FILES   ================================== */
/* ================================================================================ */ 

#include "../tle926x/TLE926x_DEFINES.h"






/* ================================================================================ */
/* ================================   MACROS   ==================================== */
/* ================================================================================ */ 

/**
 * @def              SBC_ISR_VECTOR
 *
 * @brief            Vector defining the handling of interrupts.
 *                   Vectors of this type have to be registered by the SBC_Register_Callback method.
 * @param REG        register address
 * @param MASK       mask of the designated bit or bits
 * @param POS        bit position 
 * @param COMPARE    Value to be compared with
 */
#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE)    ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE))



/**
 * \def             SBC_BITPOSITION
 * 
 * \brief           Retreives left-shift value from bit masks.
 */
#define SBC_BITPOSITION(sbc_bitmask) (__builtin_ctz(sbc_bitmask))




/* ================================================================================ */
/* =======================   General Interrupt Defines   ========================== */
/* ================================================================================ */ 



/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */
/* SUP_STAT_2 */
#define SBC_ISR_VS_UV                           SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VS_UV_MASK,     SBC_BITPOSITION(VS_UV_MASK)       ,      VS_UV_DETECTED)
#define SBC_ISR_VCC3_OC                         SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VCC3_OC_MASK,   SBC_BITPOSITION(VCC3_OC_MASK),           VCC3_OC_DETECTED)
#define SBC_ISR_VCC3_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VCC3_UV_MASK,   SBC_BITPOSITION( VCC3_UV_MASK),          VCC3_UV_FAIL_DETECTED)
#define SBC_ISR_VCC3_OT                         SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VCC3_OT_MASK,   SBC_BITPOSITION( VCC3_OT_MASK),          VCC3_OT_DETECTED)
#define SBC_ISR_VCC1_OV                         SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VCC1_OV_MASK,   SBC_BITPOSITION(VCC1_OV_MASK),           VCC1_OV_EVENT)
#define SBC_ISR_VCC1_UV_PREWARN                 SBC_ISR_VECTOR(SBC_SUP_STAT_2,      VCC1_WARN_MASK, SBC_BITPOSITION(VCC1_WARN_MASK),         VCC1_UV_PREWARN_EVENT)

/* SUP_STAT_1 */
#define SBC_ISR_POR                             SBC_ISR_VECTOR(SBC_SUP_STAT_1,      POR_MASK,        SBC_BITPOSITION(POR_MASK),              POR_EVENT)
#define SBC_ISR_VSHS_OU                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VSHS_UV_MASK,    SBC_BITPOSITION(VSHS_UV_MASK),          VSHS_UV_DETECTED)
#define SBC_ISR_VSHS_OV                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VSHS_OV_MASK,    SBC_BITPOSITION(VSHS_OV_MASK),          VSHS_OV_DETECTED)
#define SBC_ISR_VCC2_OT                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VCC2_OT_MASK,    SBC_BITPOSITION(VCC2_OT_MASK),          VCC2_OT_EVENT)
#define SBC_ISR_VCC2_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VCC2_UV_MASK,    SBC_BITPOSITION(VCC2_UV_MASK),          VCC2_UV_EVENT)
#define SBC_ISR_VCC1_SC                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VCC1_SC_MASK,    SBC_BITPOSITION(VCC1_SC_MASK),          VCC1_SC_TO_GND_EVENT)
#define SBC_ISR_VCC1_UV_FS                      SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VCC1_UV_FS_MASK, SBC_BITPOSITION(VCC1_UV_FS_MASK),       FAIL_SAFE_MODE_ENTERED)
#define SBC_ISR_VCC1_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      VCC1_UV_MASK,    SBC_BITPOSITION(VCC1_UV_MASK),          VCC1_UV_EVENT)

/* THERM_STAT */
#define SBC_ISR_TSD2_SAFESTATE                  SBC_ISR_VECTOR(SBC_THERM_STAT,      TSD2_MASK,       SBC_BITPOSITION(TSD2_MASK),             TSD2_OT_DETECTED)
#define SBC_ISR_TSD1                            SBC_ISR_VECTOR(SBC_THERM_STAT,      TSD1_MASK,       SBC_BITPOSITION(TSD1_MASK),             TSD1_OT_DETECTED)
#define SBC_ISR_TPW                             SBC_ISR_VECTOR(SBC_THERM_STAT,      TPW_MASK,        SBC_BITPOSITION(TPW_MASK),              THERMAL_PREWARNING)

/* DEV_STAT */
#define SBC_ISR_DEV_STAT                        SBC_ISR_VECTOR(SBC_DEV_STAT,        DEV_STAT_MASK,   SBC_BITPOSITION(DEV_STAT_MASK),         DEV_RESTART_AFTER_FAILURE)
#define SBC_ISR_FROM_SLEEPMODE                  SBC_ISR_VECTOR(SBC_DEV_STAT,        DEV_STAT_MASK,   SBC_BITPOSITION(DEV_STAT_MASK),         DEV_SLEEP_MODE)
#define SBC_ISR_WD_FAIL                         SBC_ISR_VECTOR(SBC_DEV_STAT,        WD_FAIL_MASK,    SBC_BITPOSITION(WD_FAIL_MASK),          WD_FAIL2)
#define SBC_ISR_SPI_FAIL                        SBC_ISR_VECTOR(SBC_DEV_STAT,        SPI_FAIL_MASK,   SBC_BITPOSITION(SPI_FAIL_MASK),         SPI_FAIL_INVALID_COMMAND_DETECTED)
#define SBC_ISR_FAILURE                         SBC_ISR_VECTOR(SBC_DEV_STAT,        FAILURE_MASK,    SBC_BITPOSITION(FAILURE_MASK),          FAILURE_OCCURED)

/* BUS_STAT_1 */
#define SBC_ISR_LIN1_FAIL_TSD                   SBC_ISR_VECTOR(SBC_BUS_STAT_1,      LIN1_FAIL_MASK,  SBC_BITPOSITION(LIN1_FAIL_MASK),        LIN_TSD_SHUTDOWN)
#define SBC_ISR_LIN1_FAIL_TXD                   SBC_ISR_VECTOR(SBC_BUS_STAT_1,      LIN1_FAIL_MASK,  SBC_BITPOSITION(LIN1_FAIL_MASK),        LIN_TXD_DOM_TIMEOUT)
#define SBC_ISR_LIN1_FAIL_BUS                   SBC_ISR_VECTOR(SBC_BUS_STAT_1,      LIN1_FAIL_MASK,  SBC_BITPOSITION(LIN1_FAIL_MASK),        LIN_BUS_DOM_TIMEOUT)
#define SBC_ISR_CANTO                           SBC_ISR_VECTOR(SBC_BUS_STAT_1,      CANTO_MASK,      SBC_BITPOSITION(CANTO_MASK),            CAN_TIMEOUT)
#define SBC_ISR_SYSERR                          SBC_ISR_VECTOR(SBC_BUS_STAT_1,      SYSERR_MASK,     SBC_BITPOSITION(SYSERR_MASK),           SYSERR_DETECTED_SWK_NOT_POSSIBLE)
#define SBC_ISR_CAN_TSD                         SBC_ISR_VECTOR(SBC_BUS_STAT_1,      CAN_FAIL_MASK,   SBC_BITPOSITION(CAN_FAIL_MASK),         CAN_TSD_SHUTDOWN)
#define SBC_ISR_CAN_TXD_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT_1,      CAN_FAIL_MASK,   SBC_BITPOSITION(CAN_FAIL_MASK),         CAN_TXD_DOM_TIMEOUT)
#define SBC_ISR_CAN_BUS_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT_1,      CAN_FAIL_MASK,   SBC_BITPOSITION(CAN_FAIL_MASK),         CAN_BUS_DOM_TIMEOUT)
#define SBC_ISR_VCAN_UV                         SBC_ISR_VECTOR(SBC_BUS_STAT_1,      VCAN_UV_MASK,    SBC_BITPOSITION(VCAN_UV_MASK),          VCAN_SUPPLY_UNDER_VOLTAGE_DETECTED)

/* BUS_STAT_2 */
#define SBC_ISR_LIN2_FAIL_TSD                   SBC_ISR_VECTOR(SBC_BUS_STAT_2,      LIN2_FAIL_MASK,  SBC_BITPOSITION(LIN2_FAIL_MASK),        LIN_TSD_SHUTDOWN)
#define SBC_ISR_LIN2_FAIL_TXD                   SBC_ISR_VECTOR(SBC_BUS_STAT_2,      LIN2_FAIL_MASK,  SBC_BITPOSITION(LIN2_FAIL_MASK),        LIN_TXD_DOM_TIMEOUT)
#define SBC_ISR_LIN2_FAIL_BUS                   SBC_ISR_VECTOR(SBC_BUS_STAT_2,      LIN2_FAIL_MASK,  SBC_BITPOSITION(LIN2_FAIL_MASK),        LIN_BUS_DOM_TIMEOUT)

/* WK_STAT_1 */
#define SBC_ISR_LIN2_WU                         SBC_ISR_VECTOR(SBC_WK_STAT_1,       LIN2_WU_MASK,    SBC_BITPOSITION(LIN2_WU_MASK),          WAKE_UP_DETECTED)
#define SBC_ISR_LIN1_WU                         SBC_ISR_VECTOR(SBC_WK_STAT_1,       LIN1_WU_MASK,    SBC_BITPOSITION(LIN1_WU_MASK),          WAKE_UP_DETECTED)
#define SBC_ISR_CAN_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_1,       CAN_WU_MASK,     SBC_BITPOSITION(CAN_WU_MASK),           WAKE_UP_DETECTED)
#define SBC_ISR_TIMER_WU                        SBC_ISR_VECTOR(SBC_WK_STAT_1,       TIMER_WU_MASK,   SBC_BITPOSITION(TIMER_WU_MASK),         WAKE_UP_DETECTED)
#define SBC_ISR_WK3_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_1,       WK3_WU_MASK,     SBC_BITPOSITION(WK3_WU_MASK),           WAKE_UP_DETECTED)
#define SBC_ISR_WK2_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_1,       WK2_WU_MASK,     SBC_BITPOSITION(WK2_WU_MASK),           WAKE_UP_DETECTED)
#define SBC_ISR_WK1_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_1,       WK1_WU_MASK,     SBC_BITPOSITION(WK1_WU_MASK),           WAKE_UP_DETECTED)

/* WK_STAT_2 */
#define SBC_ISR_GPIO2_WU                        SBC_ISR_VECTOR(SBC_WK_STAT_2,       GPIO2_WU_MASK,   SBC_BITPOSITION(GPIO2_WU_MASK),         WAKE_UP_DETECTED)
#define SBC_ISR_GPIO1_WU                        SBC_ISR_VECTOR(SBC_WK_STAT_2,       GPIO1_WU_MASK,   SBC_BITPOSITION(GPIO1_WU_MASK),         WAKE_UP_DETECTED)

/* HS_OC_OT_STAT */
#define SBC_ISR_HS4_OC_OT                       SBC_ISR_VECTOR(SBC_HS_OC_OT_STAT,   HS4_OC_OT_MASK,  SBC_BITPOSITION(HS4_OC_OT_MASK),        OC_OR_OT_DETECTED)
#define SBC_ISR_HS3_OC_OT                       SBC_ISR_VECTOR(SBC_HS_OC_OT_STAT,   HS3_OC_OT_MASK,  SBC_BITPOSITION(HS3_OC_OT_MASK),        OC_OR_OT_DETECTED)
#define SBC_ISR_HS2_OC_OT                       SBC_ISR_VECTOR(SBC_HS_OC_OT_STAT,   HS2_OC_OT_MASK,  SBC_BITPOSITION(HS2_OC_OT_MASK),        OC_OR_OT_DETECTED)
#define SBC_ISR_HS1_OC_OT                       SBC_ISR_VECTOR(SBC_HS_OC_OT_STAT,   HS1_OC_OT_MASK,  SBC_BITPOSITION(HS1_OC_OT_MASK),        OC_OR_OT_DETECTED)

/* HS_OL_STAT */
#define SBC_ISR_HS4_OL                          SBC_ISR_VECTOR(SBC_HS_OL_STAT,      HS4_OL_MASK,     SBC_BITPOSITION(HS4_OL_MASK),           OL_DETECTED)
#define SBC_ISR_HS3_OL                          SBC_ISR_VECTOR(SBC_HS_OL_STAT,      HS3_OL_MASK,     SBC_BITPOSITION(HS3_OL_MASK),           OL_DETECTED)
#define SBC_ISR_HS2_OL                          SBC_ISR_VECTOR(SBC_HS_OL_STAT,      HS2_OL_MASK,     SBC_BITPOSITION(HS2_OL_MASK),           OL_DETECTED)
#define SBC_ISR_HS1_OL                          SBC_ISR_VECTOR(SBC_HS_OL_STAT,      HS1_OL_MASK,     SBC_BITPOSITION(HS1_OL_MASK),           OL_DETECTED)

/* SWK_STAT */
#define SBC_ISR_SYNC                            SBC_ISR_VECTOR(SBC_SWK_STAT,        SYNC_MASK,       SBC_BITPOSITION(SYNC_MASK),             SYNC_VALID_FRAME_RECEIVED)
#define SBC_ISR_CANSIL                          SBC_ISR_VECTOR(SBC_SWK_STAT,        CANSIL_MASK,     SBC_BITPOSITION(CANSIL_MASK),           CANSIL_EXCEEDED)
#define SBC_ISR_SWK_SET                         SBC_ISR_VECTOR(SBC_SWK_STAT,        SWK_SET_MASK,    SBC_BITPOSITION(SWK_SET_MASK),          SWK_ACTIVE)
#define SBC_ISR_WUP                             SBC_ISR_VECTOR(SBC_SWK_STAT,        WUP_MASK,        SBC_BITPOSITION(WUP_MASK),              WUP_DETECTED)
#define SBC_ISR_WUF                             SBC_ISR_VECTOR(SBC_SWK_STAT,        WUF_MASK,        SBC_BITPOSITION(WUF_MASK),              WUF_DETECTED)

#endif  /*TLE926x_ISR_H*/
